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Entry  27 Feb 2007, Piotr Zolnierczuk, Forum, event builder scalability 
    Reply  27 Feb 2007, Stefan Ritt, Forum, event builder scalability 
    Reply  27 Feb 2007, John M O'Donnell, Forum, event builder scalability 
       Reply  27 Feb 2007, Stefan Ritt, Forum, event builder scalability 
    Reply  02 Mar 2007, Kevin Lynch, Forum, event builder scalability 
       Reply  03 Mar 2007, Piotr Zolnierczuk, Forum, event builder scalability 
          Reply  03 Mar 2007, Stefan Ritt, Forum, event builder scalability 
Message ID: 356     Entry time: 27 Feb 2007     In reply to: 355
Author: Stefan Ritt 
Topic: Forum 
Subject: event builder scalability 
> Our bottle neck is (a) compactPCI backplane reading data from waveform digitizers
> to the frontend CPUs and (b) CPU power on the frontend CPUs to analyzer the waveforms.

I forgot to mention that our front-ends at MEG are 2.8 GHz dual Xenon with Hyperthreading.
This gives "virtual" 4 CPU cores which are really necessary for waveform calibration and
analysis. It makes use of the new multi-threading feature in the midas front-end. I run
actually 7 threads (one VME readout, 4 calibration threads, one encoding thread and the
main thread sending data to the backend. This speeds up data taking by a factor of four
compared to a single thread. So if one plans for waveform analysis in the frontend to
reduce the data, I would recommend a box with dual quad cores.
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