#include <stdio.h>#include <string.h>#include <intrins.h>#include <stdlib.h>#include "mscbemb.h"Defines | |
| #define | GET_INFO_GENERAL 0 |
| #define | GET_INFO_VARIABLE 1 |
| #define | SIZE_8BIT 1 |
| #define | SIZE_16BIT 2 |
| #define | SIZE_24BIT 3 |
| #define | SIZE_32BIT 4 |
| #define | ADDR_NONE 0 |
| #define | ADDR_NODE 1 |
| #define | ADDR_GROUP 2 |
| #define | ADDR_ALL 3 |
| #define | SEND_BYTE(_b) |
Functions | |
| void | user_init (unsigned char init) |
| void | user_write (unsigned char index) reentrant |
| unsigned char | user_read (unsigned char index) |
| void | user_loop (void) |
| void | flash_upgrade (void) |
| void | send_remote_var (unsigned char i) |
| void | setup (void) |
| unsigned char | cur_sub_addr () |
| void | interprete (void) |
| void | serial_int (void) |
| static void | send_byte (unsigned char d, unsigned char *crc) |
| static void | send_obuf (unsigned char n) |
| void | addr_node8 (unsigned char mode, unsigned char adr, unsigned char node_addr) |
| void | addr_node16 (unsigned char mode, unsigned int adr, unsigned int node_addr) |
| void | upgrade () |
| void | yield (void) |
| void | main (void) |
Variables | |
| MSCB_INFO_VAR * | variables |
| unsigned char idata | _n_sub_addr |
| char code | node_name [] |
| char code | svn_rev_main [] = "$Rev: 911 $" |
| bit | lcd_present |
| unsigned char idata | in_buf [20] |
| unsigned char idata | out_buf [8] |
| unsigned char idata | i_in |
| unsigned char idata | last_i_in |
| unsigned char idata | final_i_in |
| unsigned char idata | i_out |
| unsigned char idata | cmd_len |
| unsigned char idata | crc_code |
| unsigned char idata | addr_mode |
| unsigned char idata | n_variables |
| unsigned char idata _flkey _at_ | x80 |
| unsigned char idata n_out _at_ | x81 |
| unsigned char idata | _cur_sub_addr |
| unsigned char idata | _var_size |
| SYS_INFO | sys_info |
| unsigned char bdata | CSR |
| sbit | DEBUG_MODE = CSR ^ 0 |
| sbit | SYNC_MODE = CSR ^ 1 |
| sbit | FREEZE_MODE = CSR ^ 2 |
| sbit | WD_RESET = CSR ^ 3 |
| bit | addressed |
| bit | flash_param |
| bit | flash_program |
| bit | configured_addr |
| bit | configured_vars |
| bit | flash_allowed |
| bit | wrong_cpu |
| #define ADDR_ALL 3 |
| #define ADDR_GROUP 2 |
| #define ADDR_NODE 1 |
| #define ADDR_NONE 0 |
| #define GET_INFO_GENERAL 0 |
| #define GET_INFO_VARIABLE 1 |
| #define SEND_BYTE | ( | _b | ) |
Value:
TI0 = 0; \ DELAY_US(INTERCHAR_DELAY); \ SBUF0 = _b; \ while (TI0 == 0);
| #define SIZE_16BIT 2 |
| #define SIZE_24BIT 3 |
| #define SIZE_32BIT 4 |
| #define SIZE_8BIT 1 |
| void addr_node16 | ( | unsigned char | mode, | |
| unsigned int | adr, | |||
| unsigned int | node_addr | |||
| ) |
00545 { 00546 if (node_addr == 0xFFFF) { 00547 if (adr == node_addr) { 00548 addressed = 1; 00549 _cur_sub_addr = 0; 00550 addr_mode = mode; 00551 } else { 00552 addressed = 0; 00553 addr_mode = ADDR_NONE; 00554 } 00555 } else { 00556 if (mode == ADDR_NODE) { 00557 if (adr >= node_addr && 00558 adr < node_addr + _n_sub_addr) { 00559 00560 addressed = 1; 00561 _cur_sub_addr = adr - node_addr; 00562 addr_mode = ADDR_NODE; 00563 } else { 00564 addressed = 0; 00565 addr_mode = ADDR_NONE; 00566 } 00567 } else if (mode == ADDR_GROUP) { 00568 if (adr == node_addr) { 00569 addressed = 1; 00570 _cur_sub_addr = 0; 00571 addr_mode = ADDR_GROUP; 00572 } else { 00573 addressed = 0; 00574 addr_mode = ADDR_NONE; 00575 } 00576 } 00577 } 00578 }
| void addr_node8 | ( | unsigned char | mode, | |
| unsigned char | adr, | |||
| unsigned char | node_addr | |||
| ) |
00520 { 00521 if (mode == ADDR_NODE) { 00522 if (adr >= node_addr && 00523 adr < node_addr + _n_sub_addr) { 00524 00525 addressed = 1; 00526 _cur_sub_addr = adr - node_addr; 00527 addr_mode = ADDR_NODE; 00528 } else { 00529 addressed = 0; 00530 addr_mode = ADDR_NONE; 00531 } 00532 } else if (mode == ADDR_GROUP) { 00533 if (adr == node_addr) { 00534 addressed = 1; 00535 _cur_sub_addr = 0; 00536 addr_mode = ADDR_GROUP; 00537 } else { 00538 addressed = 0; 00539 addr_mode = ADDR_NONE; 00540 } 00541 } 00542 }
| unsigned char cur_sub_addr | ( | void | ) |
| void flash_upgrade | ( | void | ) |
| void interprete | ( | void | ) |
00581 { 00582 unsigned char crc, cmd, i, j, n, ch, a1, a2; 00583 unsigned short size; 00584 MSCB_INFO_VAR *pvar; 00585 unsigned long idata u; 00586 00587 cmd = (in_buf[0] & 0xF8); // strip length field 00588 00589 #ifdef CPU_C8051F120 00590 SFRPAGE = UART0_PAGE; // needed for SBUF0 00591 #endif 00592 00593 switch (in_buf[0]) { 00594 case CMD_ADDR_NODE8: 00595 addr_node8(ADDR_NODE, in_buf[1], sys_info.node_addr & 0xFF); 00596 break; 00597 00598 case CMD_ADDR_NODE16: 00599 addr_node16(ADDR_NODE, *(unsigned int *) &in_buf[1], sys_info.node_addr); 00600 break; 00601 00602 case CMD_ADDR_BC: 00603 addressed = 1; 00604 addr_mode = ADDR_ALL; 00605 break; 00606 00607 case CMD_ADDR_GRP8: 00608 addr_node8(ADDR_GROUP, in_buf[1], sys_info.group_addr & 0xFF); 00609 break; 00610 00611 case CMD_ADDR_GRP16: 00612 addr_node16(ADDR_GROUP, *(unsigned int *) &in_buf[1], sys_info.group_addr); 00613 break; 00614 00615 case CMD_PING8: 00616 addr_node8(ADDR_NODE, in_buf[1], sys_info.node_addr & 0xFF); 00617 if (addressed) { 00618 out_buf[0] = CMD_ACK; 00619 send_obuf(1); 00620 } 00621 break; 00622 00623 case CMD_PING16: 00624 addr_node16(ADDR_NODE, *(unsigned int *) &in_buf[1], sys_info.node_addr); 00625 if (addressed) { 00626 out_buf[0] = CMD_ACK; 00627 send_obuf(1); 00628 } 00629 break; 00630 00631 case CMD_INIT: 00632 #ifdef CPU_C8051F120 00633 SFRPAGE = LEGACY_PAGE; 00634 #endif 00635 00636 RSTSRC = 0x12; // force software and VDDmon as reset src 00637 break; 00638 00639 case CMD_GET_INFO: 00640 /* general info */ 00641 00642 ES0 = 0; // temporarily disable serial interrupt 00643 crc = 0; 00644 RS485_ENABLE = 1; 00645 00646 send_byte(CMD_ACK + 7, &crc); // send acknowledge, variable data length 00647 #ifdef HAVE_RTC 00648 send_byte(30, &crc); // send data length 00649 #else 00650 send_byte(24, &crc); // send data length 00651 #endif 00652 send_byte(PROTOCOL_VERSION, &crc); // send protocol version 00653 00654 send_byte(n_variables, &crc); // send number of variables 00655 00656 send_byte(*(((unsigned char *) &sys_info.node_addr) + 0), &crc); // send node address 00657 send_byte(*(((unsigned char *) &sys_info.node_addr) + 1), &crc); 00658 00659 send_byte(*(((unsigned char *) &sys_info.group_addr) + 0), &crc); // send group address 00660 send_byte(*(((unsigned char *) &sys_info.group_addr) + 1), &crc); 00661 00662 send_byte(*(((unsigned char *) &sys_info.svn_revision) + 0), &crc); // send svn revision 00663 send_byte(*(((unsigned char *) &sys_info.svn_revision) + 1), &crc); 00664 00665 for (i = 0; i < 16; i++) // send node name 00666 send_byte(sys_info.node_name[i], &crc); 00667 00668 #ifdef HAVE_RTC 00669 for (i = 0; i < 6 ; i++) 00670 send_byte(rtc_bread[i], &crc); 00671 #endif 00672 00673 send_byte(crc, NULL); // send CRC code 00674 00675 DELAY_US(10); 00676 RS485_ENABLE = 0; 00677 ES0 = 1; // re-enable serial interrupts 00678 break; 00679 00680 case CMD_GET_INFO + 1: 00681 /* send variable info */ 00682 00683 if (in_buf[1] < n_variables) { 00684 pvar = variables + in_buf[1]; 00685 00686 ES0 = 0; // temporarily disable serial interrupt 00687 crc = 0; 00688 RS485_ENABLE = 1; 00689 00690 send_byte(CMD_ACK + 7, &crc); // send acknowledge, variable data length 00691 send_byte(13, &crc); // send data length 00692 send_byte(pvar->width, &crc); 00693 send_byte(pvar->unit, &crc); 00694 send_byte(pvar->prefix, &crc); 00695 send_byte(pvar->status, &crc); 00696 send_byte(pvar->flags, &crc); 00697 00698 for (i = 0; i < 8; i++) // send variable name 00699 send_byte(pvar->name[i], &crc); 00700 00701 send_byte(crc, NULL); // send CRC code 00702 00703 DELAY_US(10); 00704 RS485_ENABLE = 0; 00705 ES0 = 1; // re-enable serial interrupts 00706 } else { 00707 /* just send dummy ack */ 00708 out_buf[0] = CMD_ACK; 00709 out_buf[1] = 0; 00710 send_obuf(2); 00711 } 00712 00713 break; 00714 00715 case CMD_GET_UPTIME: 00716 /* send uptime */ 00717 00718 u = uptime(); 00719 00720 out_buf[0] = CMD_ACK + 4; 00721 out_buf[1] = *(((unsigned char *)&u) + 0); 00722 out_buf[2] = *(((unsigned char *)&u) + 1); 00723 out_buf[3] = *(((unsigned char *)&u) + 2); 00724 out_buf[4] = *(((unsigned char *)&u) + 3); 00725 out_buf[5] = crc8(out_buf, 5); 00726 send_obuf(6); 00727 break; 00728 00729 case CMD_SET_ADDR: 00730 00731 if (in_buf[1] == ADDR_SET_NODE) 00732 /* complete node address */ 00733 sys_info.node_addr = *((unsigned int *) (in_buf + 2)); 00734 else if (in_buf[1] == ADDR_SET_HIGH) 00735 /* only high byte node address */ 00736 *((unsigned char *)(&sys_info.node_addr)) = *((unsigned char *) (in_buf + 2)); 00737 else if (in_buf[1] == ADDR_SET_GROUP) 00738 /* group address */ 00739 sys_info.group_addr = *((unsigned int *) (in_buf + 2)); 00740 00741 /* copy address to EEPROM */ 00742 flash_param = 1; 00743 _flkey = 0xF1; 00744 00745 break; 00746 00747 case CMD_SET_NAME: 00748 /* set node name in RAM */ 00749 for (i = 0; i < 16 && i < in_buf[1]; i++) 00750 sys_info.node_name[i] = in_buf[2 + i]; 00751 sys_info.node_name[15] = 0; 00752 00753 /* copy address to EEPROM */ 00754 flash_param = 1; 00755 _flkey = 0xF1; 00756 00757 break; 00758 00759 case CMD_SET_BAUD: 00760 led_blink(_cur_sub_addr, 1, 50); 00761 uart_init(0, in_buf[1]); 00762 break; 00763 00764 case CMD_FREEZE: 00765 FREEZE_MODE = in_buf[1]; 00766 break; 00767 00768 case CMD_SYNC: 00769 SYNC_MODE = in_buf[1]; 00770 break; 00771 00772 case CMD_SET_TIME: 00773 #ifdef HAVE_RTC 00774 led_blink(0, 1, 50); 00775 for (i=0 ; i<6 ; i++) 00776 rtc_bwrite[i] = in_buf[i+1]; 00777 rtc_set = 1; 00778 #endif 00779 break; 00780 00781 case CMD_UPGRADE: 00782 if (_cur_sub_addr != 0) 00783 n = 2; // reject upgrade for sub address 00784 else if (flash_allowed == 0) 00785 n = 3; // upgrade not yet allowed 00786 else 00787 n = 1; // positive acknowledge 00788 00789 out_buf[0] = CMD_ACK + 1; 00790 out_buf[1] = n; 00791 out_buf[2] = crc8(out_buf, 2); 00792 send_obuf(3); 00793 00794 if (n == 1) { 00795 flash_program = 1; 00796 _flkey = 0xF1; 00797 } 00798 break; 00799 00800 case CMD_FLASH: 00801 flash_param = 1; 00802 _flkey = 0xF1; 00803 break; 00804 00805 case CMD_ECHO: 00806 led_blink(0, 1, 50); 00807 out_buf[0] = CMD_ACK + 1; 00808 out_buf[1] = in_buf[1]; 00809 out_buf[2] = crc8(out_buf, 2); 00810 send_obuf(3); 00811 break; 00812 00813 } 00814 00815 if (cmd == CMD_READ) { 00816 if (in_buf[0] == CMD_READ + 1) { // single variable 00817 if (in_buf[1] < n_variables) { 00818 n = variables[in_buf[1]].width; // number of bytes to return 00819 00820 if (variables[in_buf[1]].flags & MSCBF_DATALESS) { 00821 n = user_read(in_buf[1]); // for dataless variables, user routine returns bytes 00822 out_buf[0] = CMD_ACK + 7; // and places data directly in out_buf 00823 out_buf[1] = n; 00824 00825 out_buf[2 + n] = crc8(out_buf, 2 + n); // generate CRC code 00826 00827 /* send result */ 00828 send_obuf(3 + n); 00829 00830 } else { 00831 00832 user_read(in_buf[1]); 00833 00834 ES0 = 0; // temporarily disable serial interrupt 00835 crc = 0; 00836 RS485_ENABLE = 1; 00837 00838 if (n > 6) { 00839 /* variable length buffer */ 00840 send_byte(CMD_ACK + 7, &crc); // send acknowledge, variable data length 00841 send_byte(n, &crc); // send data length 00842 00843 for (i = 0; i < n; i++) // copy user data 00844 send_byte(((char *) variables[in_buf[1]].ud)[i+_var_size*_cur_sub_addr], &crc); 00845 n++; 00846 } else { 00847 00848 send_byte(CMD_ACK + n, &crc); // send acknowledge 00849 00850 for (i = 0; i < n; i++) // copy user data 00851 send_byte(((char *) variables[in_buf[1]].ud)[i+_var_size*_cur_sub_addr], &crc); 00852 } 00853 00854 send_byte(crc, NULL); // send CRC code 00855 00856 DELAY_US(10); 00857 RS485_ENABLE = 0; 00858 ES0 = 1; // re-enable serial interrupts 00859 } 00860 } else { 00861 /* just send dummy ack to indicate error */ 00862 out_buf[0] = CMD_ACK; 00863 send_obuf(1); 00864 } 00865 00866 } else if (in_buf[0] == CMD_READ + 2) { // variable range 00867 00868 if (in_buf[1] < n_variables && in_buf[2] < n_variables && in_buf[1] <= in_buf[2]) { 00869 /* calculate number of bytes to return */ 00870 for (i = in_buf[1], size = 0; i <= in_buf[2]; i++) { 00871 user_read(i); 00872 size += variables[i].width; 00873 } 00874 00875 ES0 = 0; // temporarily disable serial interrupt 00876 crc = 0; 00877 RS485_ENABLE = 1; 00878 00879 send_byte(CMD_ACK + 7, &crc); // send acknowledge, variable data length 00880 if (size < 0x80) 00881 send_byte(size, &crc); // send data length one byte 00882 else { 00883 send_byte(0x80 | size / 0x100, &crc); // send data length two bytes 00884 send_byte(size & 0xFF, &crc); 00885 } 00886 00887 /* loop over all variables */ 00888 for (i = in_buf[1]; i <= in_buf[2]; i++) { 00889 for (j = 0; j < variables[i].width; j++) // send user data 00890 send_byte(((char *) variables[i].ud)[j+_var_size*_cur_sub_addr], &crc); 00891 } 00892 00893 send_byte(crc, NULL); // send CRC code 00894 00895 DELAY_US(10); 00896 RS485_ENABLE = 0; 00897 ES0 = 1; // re-enable serial interrupts 00898 } else { 00899 /* just send dummy ack to indicate error */ 00900 out_buf[0] = CMD_ACK; 00901 send_obuf(1); 00902 } 00903 } 00904 } 00905 00906 if (cmd == CMD_USER) { 00907 led_blink(_cur_sub_addr, 1, 50); 00908 n = user_func(in_buf + 1, out_buf + 1); 00909 out_buf[0] = CMD_ACK + n; 00910 out_buf[n + 1] = crc8(out_buf, n + 1); 00911 send_obuf(n+2); 00912 } 00913 00914 if (cmd == CMD_WRITE_NA || cmd == CMD_WRITE_ACK) { 00915 00916 /* blink LED once when writing data */ 00917 if (addr_mode == ADDR_NODE) 00918 led_blink(_cur_sub_addr, 1, 50); 00919 else 00920 for (i=0 ; i<_n_sub_addr ; i++) 00921 led_blink(i, 1, 50); 00922 00923 n = in_buf[0] & 0x07; 00924 00925 if (n == 0x07) { // variable length 00926 j = 1; 00927 n = in_buf[1]; 00928 ch = in_buf[2]; 00929 } else { 00930 j = 0; 00931 ch = in_buf[1]; 00932 } 00933 00934 n--; // data size (minus channel) 00935 00936 if (ch < n_variables) { 00937 00938 /* don't exceed variable width */ 00939 if (n > variables[ch].width) 00940 n = variables[ch].width; 00941 00942 if (addr_mode == ADDR_NODE) 00943 a1 = a2 = _cur_sub_addr; 00944 else { 00945 a1 = 0; 00946 a2 = _n_sub_addr-1; 00947 } 00948 00949 for (_cur_sub_addr = a1 ; _cur_sub_addr <= a2 ; _cur_sub_addr++) { 00950 for (i = 0; i < n; i++) 00951 if (!(variables[ch].flags & MSCBF_DATALESS)) { 00952 if (variables[ch].unit == UNIT_STRING) { 00953 if (n > 4) 00954 /* copy bytes in normal order */ 00955 ((char *) variables[ch].ud)[i + _var_size*_cur_sub_addr] = 00956 in_buf[2 + j + i]; 00957 else 00958 /* copy bytes in reverse order (got swapped on host) */ 00959 ((char *) variables[ch].ud)[i + _var_size*_cur_sub_addr] = 00960 in_buf[i_in - 2 - i]; 00961 } else 00962 /* copy LSB bytes, needed for BYTE if DWORD is sent */ 00963 ((char *) variables[ch].ud)[i + _var_size*_cur_sub_addr] = 00964 in_buf[i_in - 1 - variables[ch].width + i + j]; 00965 } 00966 00967 user_write(ch); 00968 } 00969 _cur_sub_addr = a1; // restore previous value 00970 00971 #ifdef UART1_MSCB 00972 /* mark variable to be send in main loop */ 00973 if (variables[ch].flags & MSCBF_REMOUT) 00974 var_to_send = ch; 00975 #endif 00976 00977 if (cmd == CMD_WRITE_ACK) { 00978 out_buf[0] = CMD_ACK; 00979 out_buf[1] = in_buf[i_in - 1]; 00980 send_obuf(2); 00981 } 00982 } else if (ch == 0xFF) { 00983 CSR = in_buf[2]; 00984 00985 if (cmd == CMD_WRITE_ACK) { 00986 out_buf[0] = CMD_ACK; 00987 out_buf[1] = in_buf[i_in - 1]; 00988 send_obuf(2); 00989 } 00990 } 00991 } 00992 }
| void main | ( | void | ) |
01570 { 01571 setup(); 01572 01573 // Code lock code 01574 //-PAA- 01575 // SFRPAGE = CONFIG_PAGE; 01576 // FLACL = 32; // 32 * 1024 bytes 01577 01578 do { 01579 yield(); 01580 01581 #ifdef UART1_MSCB 01582 manage_remote_vars(); 01583 #endif 01584 01585 user_loop(); 01586 01587 } while (1); 01588 01589 }
| static void send_byte | ( | unsigned char | d, | |
| unsigned char * | crc | |||
| ) | [static] |
00493 { 00494 #ifdef CPU_C8051F120 00495 SFRPAGE = UART0_PAGE; 00496 #endif 00497 00498 if (crc) 00499 *crc = crc8_add(*crc, d); 00500 DELAY_US(INTERCHAR_DELAY); 00501 SBUF0 = d; 00502 watchdog_refresh(1); 00503 while (!TI0); 00504 TI0 = 0; 00505 }
| static void send_obuf | ( | unsigned char | n | ) | [static] |
00508 { 00509 #ifdef CPU_C8051F120 00510 SFRPAGE = UART0_PAGE; 00511 #endif 00512 00513 n_out = n; 00514 RS485_ENABLE = 1; 00515 DELAY_US(INTERCHAR_DELAY); 00516 SBUF0 = out_buf[0]; 00517 }
| void send_remote_var | ( | unsigned char | i | ) |
| void serial_int | ( | void | ) |
00416 { 00417 if (TI0) { 00418 /* character has been transferred */ 00419 00420 TI0 = 0; // clear TI flag 00421 00422 i_out++; // increment output counter 00423 if (i_out == n_out) { 00424 i_out = n_out = 0; // send buffer empty, clear pointer 00425 DELAY_US(10); 00426 RS485_ENABLE = 0; // disable RS485 driver 00427 } else { 00428 DELAY_US(INTERCHAR_DELAY); 00429 SBUF0 = out_buf[i_out]; // send character 00430 } 00431 } 00432 00433 if (RI0) { 00434 /* character has been received */ 00435 00436 if (!RB80 && !addressed) { 00437 RI0 = 0; 00438 i_in = 0; 00439 return; // discard data if not bit9 and not addressed 00440 } 00441 00442 RB80 = 0; 00443 in_buf[i_in++] = SBUF0; 00444 RI0 = 0; 00445 00446 if (i_in == 1) { 00447 /* check for padding character */ 00448 if (in_buf[0] == 0) { 00449 i_in = 0; 00450 return; 00451 } 00452 00453 /* initialize command length if first byte */ 00454 cmd_len = (in_buf[0] & 0x07) + 2; // + cmd + crc 00455 } 00456 00457 if (i_in == 2 && cmd_len == 9) { 00458 /* variable length command */ 00459 cmd_len = in_buf[1] + 3; // + cmd + N + crc 00460 } 00461 00462 if (i_in == sizeof(in_buf)) { // check for buffer overflow 00463 i_in = 0; 00464 return; // don't interprete command 00465 } 00466 00467 if (i_in < cmd_len) // return if command not yet complete 00468 return; 00469 00470 if (in_buf[i_in - 1] != crc8(in_buf, i_in - 1)) { 00471 i_in = 0; 00472 return; // return if CRC code does not match 00473 } 00474 00475 DELAY_US(INTERCHAR_DELAY); 00476 00477 interprete(); // interprete command 00478 i_in = 0; 00479 } 00480 }
| void setup | ( | void | ) |
00118 { 00119 unsigned char adr, flags, d; 00120 unsigned short i; 00121 unsigned char *p; 00122 00123 _flkey = 0; 00124 00125 /* first disable watchdog */ 00126 watchdog_disable(); 00127 00128 /* Port and oscillator configuration */ 00129 00130 #if defined(CPU_C8051F120) 00131 00132 SFRPAGE = CONFIG_PAGE; 00133 00134 #ifdef FEB64 00135 XBR0 = 0x05; // Enable SMBus, UART0 00136 XBR1 = 0x00; 00137 XBR2 = 0x40; // Enable Xbar 00138 P1MDOUT = 0x08; // ResetN in PP 00139 #else 00140 XBR0 = 0x04; // Enable UART0 00141 XBR1 = 0x00; 00142 XBR2 = 0x44; // Enable Xbar & UART1 00143 #endif 00144 #ifdef LOADER 00145 #if defined(L_TEMP36) || defined (L_LPB) 00146 XBR0 = 0x04; // Enable SMBus, UART0 00147 #else 00148 XBR0 = 0x05; // Enable only UART0 00149 #endif 00150 XBR1 = 0x00; 00151 XBR2 = 0x40; // Enable Xbar 00152 P1MDOUT = 0x08; // ResetN in PP 00153 RS485_ENABLE = 0; // disable RS485 driver 00154 // DEBUG_PIN = 0; 00155 #endif 00156 #ifdef CMB 00157 XBR0 = 0x04; // Enable UART0 00158 XBR1 = 0x00; 00159 XBR2 = 0x40; // Enable Xbar 00160 #endif 00161 #ifdef TEMP36 00162 XBR0 = 0x04; // Enable UART0 00163 XBR1 = 0x00; 00164 XBR2 = 0x40; // Enable Xbar 00165 00166 // run TEMP36 at 6.1 MHz 00167 SFRPAGE = CONFIG_PAGE; 00168 OSCICN = 0x81; // divide by 4 00169 CLKSEL = 0x00; // select internal oscillator 00170 #endif 00171 00172 #ifdef TREVAL_12X 00173 XBR1 = 0x00; // Sysclk (0x80) Disable 00174 XBR2 = 0x40; // UART1 Disable 00175 P0MDOUT |= 0x4; // P0.2: RS485_ENABLE 00176 P1MDOUT = 0x60; // P1.6..7 : Pushpull LED 00177 RS485_ENABLE = 0; // disable RS485 driver 00178 #endif 00179 00180 #ifdef SCS_210 // run SCS_210 at 24.5 MHz 00181 /* Select internal quartz oscillator */ 00182 SFRPAGE = LEGACY_PAGE; 00183 FLSCL = 0x00; // set flash read time for <25 MHz 00184 00185 SFRPAGE = CONFIG_PAGE; 00186 OSCICN = 0x83; // divide by 1 00187 CLKSEL = 0x00; // select internal oscillator 00188 #else // run SCS_1001 at 98 MHz 00189 /* Select internal quartz oscillator */ 00190 SFRPAGE = LEGACY_PAGE; 00191 FLSCL = 0xB0; // set flash read time for 100 MHz 00192 00193 SFRPAGE = CONFIG_PAGE; 00194 OSCICN = 0x83; // divide by 1 00195 CLKSEL = 0x00; // select internal oscillator 00196 00197 PLL0CN |= 0x01; 00198 PLL0DIV = 0x01; 00199 PLL0FLT = 0x01; 00200 PLL0MUL = 0x04; 00201 for (i = 0 ; i < 15; i++); // Wait 5us for initialization 00202 PLL0CN |= 0x02; 00203 for (i = 0 ; i<50000 && ((PLL0CN & 0x10) == 0) ; i++); 00204 00205 CLKSEL = 0x02; // select PLL as sysclk src 00206 #endif 00207 00208 #elif defined(CPU_C8051F020) 00209 00210 XBR0 = 0x04; // Enable UART0 & UART1 00211 XBR1 = 0x00; 00212 XBR2 = 0x44; 00213 00214 P0MDOUT = 0x01; // P0.0: TX = Push Pull 00215 P1MDOUT = 0x00; // P1: LPT 00216 P2MDOUT = 0x00; // P2: LPT 00217 P3MDOUT = 0xE0; // P3.5,6,7: Optocouplers 00218 00219 #ifdef SCS_220 00220 P0MDOUT |= 0x40; // P0.6: RS485_SEC_ENABLE = Push Pull 00221 #endif 00222 00223 /* Select external quartz oscillator */ 00224 OSCXCN = 0x67; // Crystal mode, Power Factor 22E6 00225 OSCICN = 0x08; // CLKSL=1 (external) 00226 00227 #elif defined(CPU_C8051F310) || defined(CPU_C8051F320) || defined(CPU_C8051F410) 00228 00229 XBR0 = 0x01; // Enable RX/TX 00230 XBR1 = 0x40; // Enable crossbar 00231 00232 #ifdef SCS_320 00233 P0MDOUT = 0x18; // P0.3:TX, P0.4:RS485 enable Push/Pull 00234 #else 00235 #ifdef CPU_C8051F410 00236 P0MDOUT = 0x50; // P0.4:TX, P0.6:RS485 enable Push/Pull 00237 #else 00238 P0MDOUT = 0x90; // P0.4:TX, P0.7:RS485 enable Push/Pull 00239 #endif 00240 00241 #endif 00242 /* Select internal quartz oscillator */ 00243 #ifdef CPU_C8051F410 00244 OSCICN = 0x87; // IOSCEN=1, SYSCLK=24.5 MHz 00245 #else 00246 OSCICN = 0x83; // IOSCEN=1, SYSCLK=24.5 MHz 00247 #endif 00248 CLKSEL = 0x00; // derive SYSCLK from internal source 00249 00250 #else 00251 00252 XBR0 = 0x04; // Enable RX/TX 00253 XBR1 = 0x00; // 00254 XBR2 = 0x40; // Enable crossbar 00255 00256 PRT0CF = 0x01; // P0.0: TX = Push Pull 00257 PRT1CF = 0x00; // P1 00258 PRT2CF = 0x00; // P2 Open drain for 5V LCD 00259 PRT3CF = 0x20; // P3.5: RS485 enable = Push Pull 00260 00261 /* Select external quartz oscillator */ 00262 OSCXCN = 0x67; // Crystal mode, Power Factor 22E6 00263 OSCICN = 0x08; // CLKSL=1 (external) 00264 00265 #endif 00266 00267 /* start system clock */ 00268 sysclock_init(); 00269 00270 /* enable watchdog with default timeout */ 00271 // watchdog_enable(0); 00272 00273 /* default LED mode */ 00274 for (i=0 ; i<N_LED ; i++) 00275 led_mode(i, 1); 00276 00277 /* initialize all memory */ 00278 CSR = 0; 00279 addressed = 0; 00280 flash_param = 0; 00281 flash_program = 0; 00282 flash_allowed = 0; 00283 wrong_cpu = 0; 00284 _flkey = 0; 00285 00286 #ifdef HAVE_RTC 00287 rtc_set = 0; 00288 #ifdef TEMP36 //NW 00289 SFRPAGE = CONFIG_PAGE; 00290 P0MDOUT |= 0x60; //Set the RTC CE to be push/pull 00291 P2MDOUT |= 0x10; //Set the SCLK line to be push/pull 00292 rtc_init(); //No write protection 00293 rtc_write_byte(0x90,0xA5); //Charges the supercap, uses 2k ohm resistor and 1 diode 00294 #endif 00295 #endif 00296 00297 RS485_ENABLE = 0; 00298 i_in = i_out = n_out = 0; 00299 _cur_sub_addr = 0; 00300 for (i=0 ; i<sizeof(in_buf) ; i++) 00301 in_buf[i] = 0; 00302 for (i=0 ; i<sizeof(out_buf) ; i++) 00303 out_buf[i] = 0; 00304 00305 /* check if we got reset by watchdog */ 00306 #if defined(CPU_C8051F120) 00307 SFRPAGE = LEGACY_PAGE; 00308 #endif 00309 WD_RESET = ((RSTSRC & 0x02) == 0 && (RSTSRC & 0x08) > 0); 00310 00311 /* initialize UART(s) */ 00312 uart_init(0, BD_115200); 00313 00314 #ifdef UART1_MSCB 00315 uart_init(1, BD_115200); 00316 #endif 00317 00318 #ifdef HAVE_LCD 00319 lcd_setup(); 00320 #endif 00321 00322 #ifdef DYN_VARIABLES 00323 setup_variables(); 00324 #endif 00325 00326 /* count variables */ 00327 for (n_variables = _var_size = 0;; n_variables++) { 00328 _var_size += variables[n_variables].width; 00329 if (variables[n_variables].width == 0) 00330 break; 00331 } 00332 00333 /* check if variables are in xdata and xdata is present */ 00334 if (n_variables > 0) { 00335 p = variables[0].ud; 00336 d = *p; 00337 *p = 0x55; 00338 if (*p != 0x55) 00339 wrong_cpu = 1; 00340 *p = 0xAA; 00341 if (*p != 0xAA) 00342 wrong_cpu = 1; 00343 *p = d; 00344 } 00345 00346 /* retrieve EEPROM data */ 00347 #ifdef CPU_C8051F120 00348 SFRPAGE = LEGACY_PAGE; 00349 #endif 00350 if ((RSTSRC & 0x02) > 0) 00351 flags = eeprom_retrieve(1); // vars on cold start 00352 else 00353 flags = eeprom_retrieve(0); 00354 00355 if ((flags & (1 << 0)) == 0) { 00356 configured_addr = 0; 00357 00358 /* set initial values */ 00359 sys_info.node_addr = 0xFFFF; 00360 sys_info.group_addr = 0xFFFF; 00361 memset(sys_info.node_name, 0, sizeof(sys_info.node_name)); 00362 strncpy(sys_info.node_name, node_name, sizeof(sys_info.node_name)); 00363 } else 00364 configured_addr = 1; 00365 00366 /* store SVN revision */ 00367 sys_info.svn_revision = (svn_rev_main[6]-'0')*1000+ 00368 (svn_rev_main[7]-'0')*100+ 00369 (svn_rev_main[8]-'0')*10+ 00370 (svn_rev_main[9]-'0'); 00371 00372 if ((flags & (1 << 1)) == 0) { 00373 00374 /* init variables */ 00375 for (i = 0; variables[i].width; i++) 00376 if (!(variables[i].flags & MSCBF_DATALESS)) { 00377 /* do it for each sub-address */ 00378 for (adr = 0 ; adr < _n_sub_addr ; adr++) { 00379 memset((char*)variables[i].ud + _var_size*adr, 0, variables[i].width); 00380 } 00381 } 00382 00383 /* call user initialization routine with initialization */ 00384 user_init(1); 00385 00386 /* write current variables to flash later in main routine */ 00387 configured_vars = 0; 00388 } else { 00389 /* call user initialization routine without initialization */ 00390 user_init(0); 00391 configured_vars = 1; 00392 } 00393 00394 /* Blink LEDs */ 00395 for (i=0 ; i<N_LED ; i++) 00396 led_blink(i, 3, 150); 00397 00398 }
| void upgrade | ( | ) |
01149 { 01150 unsigned char cmd, page, crc, j, k; 01151 unsigned short i; 01152 unsigned char xdata *pw; 01153 unsigned char code *pr; 01154 01155 if (_flkey != 0xF1) 01156 return; 01157 01158 /* wait for acknowledge to be sent */ 01159 for (i=0 ; i<10000 ; i++) { 01160 if (n_out == 0) 01161 break; 01162 DELAY_US(10); 01163 } 01164 01165 /* disable all interrupts */ 01166 EA = 0; 01167 #if defined(CPU_C8051F120) 01168 SFRPAGE = UART1_PAGE; 01169 SCON1 &= ~0x03; // clear pending UART1 interrupts 01170 #endif 01171 01172 /* disable watchdog */ 01173 #if defined(CPU_C8051F310) || defined(CPU_C8051F320) || defined(CPU_C8051F410) 01174 PCA0MD = 0x00; 01175 #else 01176 WDTCN = 0xDE; 01177 WDTCN = 0xAD; 01178 #endif 01179 01180 cmd = page = 0; 01181 01182 do { 01183 01184 receive_cmd: 01185 01186 #ifdef CPU_C8051F120 01187 SFRPAGE = UART0_PAGE; 01188 #endif 01189 01190 /* receive command */ 01191 while (!RI0) { 01192 for (i=0 ; !RI0 && i<5000 ; i++) 01193 DELAY_US(10); 01194 led_0 = !led_0; 01195 #ifdef EXT_WATCHDOG 01196 EXT_WATCHDOG_PIN = !EXT_WATCHDOG_PIN; 01197 #endif 01198 } 01199 01200 cmd = SBUF0; 01201 RI0 = 0; 01202 01203 #ifdef EXT_WATCHDOG 01204 EXT_WATCHDOG_PIN = !EXT_WATCHDOG_PIN; 01205 #endif 01206 01207 /* cannot use case since it calls the C library */ 01208 01209 if (cmd == CMD_PING16) { 01210 01211 for (i=0 ; !RI0 && i < 5000 ; i++) 01212 DELAY_US(10); 01213 if (!RI0) 01214 goto receive_cmd; 01215 page = SBUF0; // LSB 01216 RI0 = 0; 01217 for (i=0 ; !RI0 && i < 5000 ; i++) 01218 DELAY_US(10); 01219 if (!RI0) 01220 goto receive_cmd; 01221 page = SBUF0; // MSB 01222 RI0 = 0; 01223 for (i=0 ; !RI0 && i < 5000 ; i++) 01224 DELAY_US(10); 01225 if (!RI0) 01226 goto receive_cmd; 01227 page = SBUF0; // CRC 01228 RI0 = 0; 01229 01230 /* acknowledge ping, independent of own address */ 01231 RS485_ENABLE = 1; 01232 SEND_BYTE(CMD_ACK); 01233 DELAY_US(10); 01234 RS485_ENABLE = 0; 01235 01236 } else if (cmd == CMD_UPGRADE) { 01237 01238 for (i=0 ; !RI0 && i < 5000 ; i++) 01239 DELAY_US(10); 01240 if (!RI0) 01241 goto receive_cmd; 01242 page = SBUF0; // CRC 01243 RI0 = 0; 01244 01245 /* acknowledge upgrade */ 01246 RS485_ENABLE = 1; 01247 SEND_BYTE(CMD_ACK+1); 01248 SEND_BYTE(1); 01249 SEND_BYTE(0); // dummy CRC 01250 DELAY_US(10); 01251 RS485_ENABLE = 0; 01252 01253 } else if (cmd == UCMD_ECHO) { 01254 01255 RS485_ENABLE = 1; 01256 SEND_BYTE(CMD_ACK); 01257 SEND_BYTE(0); // dummy CRC, needed by subm_250 01258 DELAY_US(10); 01259 RS485_ENABLE = 0; 01260 01261 } else if (cmd == UCMD_ERASE) { 01262 01263 /* receive page */ 01264 for (i=0 ; !RI0 && i < 5000 ; i++) 01265 DELAY_US(10); 01266 if (!RI0) 01267 goto receive_cmd; 01268 01269 page = SBUF0; 01270 RI0 = 0; 01271 crc = 0; 01272 01273 led_0 = !(page & 1); 01274 01275 /* erase page if not page of upgrade() function */ 01276 if (page*512 < (unsigned int)upgrade && page*512 < EEPROM_OFFSET) { 01277 01278 #ifdef CPU_C8051F120 01279 /* for F120, only erase even pages (1024kB page size!) */ 01280 if (page & 1) 01281 goto erase_ok; 01282 01283 SFRPAGE = LEGACY_PAGE; 01284 #endif 01285 01286 #if defined(CPU_C8051F000) 01287 FLSCL = (FLSCL & 0xF0) | 0x08; // set timer for 11.052 MHz clock 01288 #elif defined (CPU_C8051F020) || defined(CPU_C8051F120) 01289 FLSCL = FLSCL | 1; // enable flash writes 01290 #endif 01291 PSCTL = 0x03; // allow write and erase 01292 01293 pw = (char xdata *) (512 * page); 01294 01295 #if defined(CPU_C8051F310) || defined (CPU_C8051F320) || defined(CPU_C8051F410) 01296 FLKEY = 0xA5; // write flash key code 01297 FLKEY = _flkey; 01298 #endif 01299 01300 #if defined(CPU_c8051F410) 01301 VDM0CN = 0xA0; 01302 RSTSRC = 0x02; 01303 #endif 01304 *pw = 0; // Initiale erase page (512 bytes) 01305 01306 #if !defined(CPU_C8051F310) && !defined(CPU_C8051F320) && !defined(CPU_C8051F410) 01307 FLSCL = (FLSCL & 0xF0); 01308 #endif 01309 PSCTL = 0x00; 01310 01311 } else { 01312 crc = 0xFF; // return 'protected' flag 01313 } 01314 01315 #ifdef CPU_C8051F120 01316 SFRPAGE = UART0_PAGE; 01317 #endif 01318 01319 #ifdef CPU_C8051F120 01320 erase_ok: 01321 #endif 01322 /* return acknowledge */ 01323 RS485_ENABLE = 1; 01324 SEND_BYTE(CMD_ACK); 01325 SEND_BYTE(crc); 01326 DELAY_US(10); 01327 RS485_ENABLE = 0; 01328 01329 } else if (cmd == UCMD_PROGRAM) { 01330 01331 /* receive page */ 01332 for (i=0 ; !RI0 && i < 5000 ; i++) 01333 DELAY_US(10); 01334 if (!RI0) 01335 goto receive_cmd; 01336 page = SBUF0; 01337 RI0 = 0; 01338 01339 /* receive subpage */ 01340 for (i=0 ; !RI0 && i < 5000 ; i++) 01341 DELAY_US(10); 01342 if (!RI0) 01343 goto receive_cmd; 01344 j = SBUF0; 01345 RI0 = 0; 01346 01347 led_0 = page & 1; 01348 01349 /* program page if not page of upgrade() function */ 01350 if (page*512 >= (unsigned int)upgrade || page*512 >= EEPROM_OFFSET) 01351 goto receive_cmd; 01352 01353 #ifdef CPU_C8051F120 01354 SFRPAGE = LEGACY_PAGE; 01355 #endif 01356 01357 /* allow write */ 01358 #if defined(CPU_C8051F000) 01359 FLSCL = (FLSCL & 0xF0) | 0x08; // set timer for 11.052 MHz clock 01360 #elif defined (CPU_C8051F020) || defined(CPU_C8051F120) 01361 FLSCL = FLSCL | 1; // enable flash writes 01362 #endif 01363 PSCTL = 0x01; // allow write access 01364 01365 pw = (char xdata *) (page*512 + j*32); 01366 01367 #ifdef CPU_C8051F120 01368 SFRPAGE = UART0_PAGE; 01369 #endif 01370 01371 /* receive 32 bytes */ 01372 for (k = 0; k < 32; k++) { 01373 for (i=0 ; !RI0 && i < 5000 ; i++) 01374 DELAY_US(10); 01375 if (!RI0) 01376 goto receive_cmd; 01377 01378 #if defined(CPU_C8051F310) || defined (CPU_C8051F320) || defined(CPU_C8051F410) 01379 FLKEY = 0xA5; // write flash key code 01380 FLKEY = _flkey; 01381 #endif 01382 #if defined(CPU_c8051F410) 01383 VDM0CN = 0xA0; 01384 RSTSRC = 0x02; 01385 #endif 01386 /* flash byte */ 01387 *pw++ = SBUF0; 01388 RI0 = 0; 01389 } 01390 01391 #ifdef CPU_C8051F120 01392 SFRPAGE = LEGACY_PAGE; 01393 #endif 01394 01395 /* disable write */ 01396 #if !defined(CPU_C8051F310) && !defined(CPU_C8051F320) && !defined(CPU_C8051F410) 01397 FLSCL = (FLSCL & 0xF0); 01398 #endif 01399 PSCTL = 0x00; 01400 01401 #ifdef CPU_C8051F120 01402 SFRPAGE = UART0_PAGE; 01403 #endif 01404 01405 RS485_ENABLE = 1; 01406 SEND_BYTE(CMD_ACK); 01407 SEND_BYTE(0); 01408 DELAY_US(10); 01409 RS485_ENABLE = 0; 01410 01411 } else if (cmd == UCMD_VERIFY) { 01412 01413 /* receive page */ 01414 for (i=0 ; !RI0 && i < 5000 ; i++) 01415 DELAY_US(10); 01416 if (!RI0) 01417 goto receive_cmd; 01418 01419 page = SBUF0; 01420 RI0 = 0; 01421 01422 pr = 512 * page; 01423 01424 /* return simplified CRC */ 01425 for (i = crc = 0; i < 512; i++) 01426 crc += *pr++; 01427 01428 /* return acknowledge */ 01429 RS485_ENABLE = 1; 01430 SEND_BYTE(CMD_ACK); 01431 SEND_BYTE(crc); 01432 DELAY_US(10); 01433 RS485_ENABLE = 0; 01434 01435 } else if (cmd == UCMD_READ) { 01436 01437 /* receive page */ 01438 for (i=0 ; !RI0 && i < 5000 ; i++) 01439 DELAY_US(10); 01440 if (!RI0) 01441 goto receive_cmd; 01442 page = SBUF0; 01443 RI0 = 0; 01444 01445 /* receive subpage */ 01446 for (i=0 ; !RI0 && i < 5000 ; i++) 01447 DELAY_US(10); 01448 if (!RI0) 01449 goto receive_cmd; 01450 j = SBUF0; 01451 RI0 = 0; 01452 01453 RS485_ENABLE = 1; 01454 01455 SEND_BYTE(CMD_ACK+7); // send acknowledge, variable data length 01456 SEND_BYTE(32); // send data length 01457 01458 pr = (512 * page + 32 * j); 01459 01460 /* send 32 bytes */ 01461 for (k = crc = 0 ; k<32 ; k++) { 01462 SEND_BYTE(*pr); 01463 crc += *pr++; 01464 } 01465 01466 SEND_BYTE(crc); 01467 DELAY_US(10); 01468 RS485_ENABLE = 0; 01469 01470 } else if (cmd == UCMD_REBOOT) { 01471 01472 #ifdef CPU_C8051F120 01473 SFRPAGE = LEGACY_PAGE; 01474 #endif 01475 RSTSRC = 0x12; // Force soft reset and VDDmon as reset src 01476 } 01477 01478 } while (cmd != UCMD_RETURN); 01479 01480 01481 _flkey = 0; 01482 EA = 1; // re-enable interrupts 01483 }
| void user_init | ( | unsigned char | init | ) |
00183 { 00184 char xdata i; 00185 /* Format the SVN and store this code SVN revision into the system */ 00186 for (i = 0; i < 4; i++) { 00187 if (svn_rev_code[6 + i] < 48) { 00188 svn_rev_code[6 + i] = '0'; 00189 } 00190 } 00191 sys_info.svn_revision = (svn_rev_code[6] - '0') * 1000 + 00192 (svn_rev_code[7] - '0') * 100 + 00193 (svn_rev_code[8] - '0') * 10 + 00194 (svn_rev_code[9] - '0'); 00195 00196 // P0MDIN = 0xFF; // default 0xFF all digital pins 00197 // P1MDIN = 0xFF; 00198 // P2MDIN = 0xFF; 00199 00200 P0MDOUT = 0x18; // Default OD 485TX, TXD 00201 P1MDOUT = 0x00; // OD 00202 P2MDOUT = 0xFF; // OD 00203 00204 P0 = 0x03; // default 0xFF 00205 P1 = 0xFF; 00206 P2 = 0xFF; 00207 00208 /* set initial state of lines */ 00209 GPIB_DATA = 0xFF; 00210 GPIB_EOI = 1; 00211 GPIB_DAV = 1; 00212 GPIB_NRFD = 1; 00213 GPIB_NDAC = 1; 00214 GPIB_IFC = 1; 00215 GPIB_SRQ = 1; 00216 GPIB_ATN = 1; 00217 GPIB_REN = 1; 00218 00219 BUF_CLE = 0; // Enable buffers 00220 BUF_DATAE = 0; 00221 00222 /* initialize GPIB */ 00223 GPIB_IFC = 0; 00224 delay_ms (1); 00225 GPIB_IFC = 1; 00226 00227 GPIB_ATN = 0; 00228 send_byte (0x14); // DCL 00229 GPIB_ATN = 1; 00230 00231 user_data.gpib_adr = GPIB_ADDR_0; 00232 00233 sprintf (str, "OE2"); // prohibit overvoltage setting 00234 send (user_data.gpib_adr, str); 00235 sprintf (str, "OC0"); // hv supply will *not* shutdown if current overload 00236 send (user_data.gpib_adr, str); 00237 sprintf (str, "SE0"); // enables SRQ in response to overvoltage detection 00238 send (user_data.gpib_adr, str); 00239 sprintf (str, "SC0"); // enables SRQ in response to overcurrent detection 00240 send (user_data.gpib_adr, str); 00241 00242 user_data.status = 0; 00243 if (init) { 00244 user_data.ramp_up = 10; 00245 user_data.ramp_down = 10; 00246 user_data.u_limit = MAX_VOLTAGE; 00247 user_data.i_limit = MAX_CURRENT; 00248 } 00249 sprintf (user_data.warning, "current OK"); 00250 00251 set_voltage_limit(user_data.u_limit); 00252 set_current_limit(user_data.i_limit); 00253 00254 read_hvi(); // check to see if hv is already on 00255 00256 if ( user_data.u_meas < 10 ) // bertan hv must be off 00257 { 00258 user_data.u_demand = 0; 00259 u_actual = 0; 00260 set_hv(0); 00261 } 00262 else // bertan hv must already be on 00263 { 00264 user_data.u_demand = user_data.u_meas; // restore to status quo 00265 u_actual = user_data.u_meas; 00266 } 00267 00268 #ifdef RTC_410 00269 // Init RTC on 410 00270 SmaRTCInit(); 00271 #endif 00272 }
| void user_loop | ( | void | ) |
00683 { 00684 /* set voltage limit if changed */ 00685 if (chn_bits & HV_LIMIT_CHANGED) { 00686 set_voltage_limit(user_data.u_limit); 00687 chn_bits &= ~HV_LIMIT_CHANGED; 00688 } 00689 00690 /* set current limit if changed */ 00691 if (chn_bits & CUR_LIMIT_CHANGED) { 00692 set_current_limit(user_data.i_limit); 00693 chn_bits &= ~CUR_LIMIT_CHANGED; 00694 } 00695 00696 // Read Voltage and Current 00697 read_hvi(); 00698 00699 // Yield to other activities (MSCB) 00700 // yield(); 00701 00702 // Do ramping if necessary 00703 ramp_hv(); 00704 00705 #ifdef RTC_410 00706 // RTC stuff 00707 ltime = SmaRTCRead(); 00708 user_data.mytime = ltime; 00709 ascTime(mydate, ltime); 00710 sprintf(user_data.date, "%s", mydate); 00711 #endif 00712 00713 // Slow it down 00714 delay_ms (MINDEL); 00715 00716 // Loop timing 00717 led_blink(0, 1, 50); 00718 }
| void user_write | ( | unsigned char | index | ) |
00387 { 00388 rCSR = user_data.status; 00389 if (index == IDXCTL) { 00390 rCTL = user_data.control; 00391 } // IDXCTL 00392 00393 // 00394 //-- EE Page function 00395 if (index == IDXEEP_CTL) EEP_CTR_Flag = 1; 00396 }
| void yield | ( | void | ) |
01497 { 01498 watchdog_refresh(0); 01499 01500 /* output RS232 data if present */ 01501 #if defined(UART1_DEVICE) 01502 rs232_output(); 01503 #endif 01504 /* blink LED if not configured */ 01505 if (!configured_addr) 01506 led_blink(0, 1, 50); 01507 01508 /* blink LED if wrong CPU */ 01509 if (wrong_cpu) 01510 led_blink(0, 1, 30); 01511 01512 /* flash EEPROM if asked by interrupt routine, wait 3 sec 01513 after reboot (power might not be stable) */ 01514 if (flash_param && flash_allowed) { 01515 led_blink(_cur_sub_addr, 1, 50); 01516 01517 flash_param = 0; 01518 01519 eeprom_flash(); 01520 configured_addr = 1; 01521 } 01522 01523 /* flash EEPROM if variables just got initialized */ 01524 if (!configured_vars && flash_allowed) { 01525 _flkey = 0xF1; 01526 eeprom_flash(); 01527 configured_vars = 1; 01528 } 01529 01530 if (flash_program && flash_allowed) { 01531 flash_program = 0; 01532 01533 #ifdef HAVE_LCD 01534 lcd_clear(); 01535 lcd_goto(0, 0); 01536 puts(" Upgrading"); 01537 lcd_goto(0, 1); 01538 puts(" Firmware..."); 01539 #endif 01540 01541 /* go to "bootloader" program */ 01542 upgrade(); 01543 } 01544 01545 #ifdef HAVE_RTC 01546 if (rtc_set) { 01547 rtc_write(rtc_bwrite); 01548 rtc_set = 0; 01549 } 01550 01551 if (time() > rtc_last+90 || time() < rtc_last) { 01552 rtc_last = time(); 01553 rtc_read(rtc_bread); 01554 } 01555 #endif 01556 01557 /* allow flash 3 sec after reboot */ 01558 if (!flash_allowed && time() > 300) 01559 flash_allowed = 1; 01560 01561 }
| unsigned char idata _cur_sub_addr |
| unsigned char idata _n_sub_addr |
| unsigned char idata _var_size |
| unsigned char idata addr_mode |
| bit addressed |
| unsigned char idata cmd_len |
| bit configured_addr |
| bit configured_vars |
| unsigned char idata crc_code |
| unsigned char bdata CSR |
| sbit DEBUG_MODE = CSR ^ 0 |
| unsigned char idata final_i_in |
| bit flash_allowed |
| bit flash_param |
| bit flash_program |
| sbit FREEZE_MODE = CSR ^ 2 |
| unsigned char idata i_in |
| unsigned char idata i_out |
| unsigned char idata in_buf[20] |
| unsigned char idata last_i_in |
| bit lcd_present |
| unsigned char idata n_variables |
| char code node_name[] |
| unsigned char idata out_buf[8] |
| char code svn_rev_main[] = "$Rev: 911 $" |
| bit wrong_cpu |
| unsigned char idata n_out _at_ x81 |
1.4.7