/home/daqweb/fgddaq/c8051/mscbutil.c File Reference

#include <intrins.h>
#include <string.h>
#include <stdio.h>
#include "mscbemb.h"

Defines

#define DEFAULT_WATCHDOG_TIMEOUT   10

Functions

unsigned char crc8 (unsigned char *buffer, int len) reentrant
unsigned char crc8_add (unsigned char crc, unsigned int c)
void uart_init (unsigned char port, unsigned char baud)
void sysclock_reset (void)
void sysclock_init (void)
void led_int ()
void tcp_timer (void)
void watchdog_int (void)
void led_mode (unsigned char led, unsigned char flag) reentrant
void led_blink (unsigned char led, unsigned char n, int interval) reentrant
void led_set (unsigned char led, unsigned char flag) reentrant
unsigned long time (void)
unsigned long uptime (void)
void watchdog_refresh (unsigned char from_interrupt) reentrant
void watchdog_enable (unsigned char timeout)
void watchdog_disable (void)
void delay_ms (unsigned int ms)
void delay_us (unsigned int us)
void eeprom_read (void *dst, unsigned char len, unsigned short *offset)
void eeprom_write (void *src, unsigned char len, unsigned short *offset)
void eeprom_erase (void)
void eeprom_flash (void)
unsigned char eeprom_retrieve (unsigned char flag)

Variables

SYS_INFO sys_info
MSCB_INFO_VARvariables
unsigned char idata _n_sub_addr
unsigned char idata _var_size
unsigned char idata _flkey
unsigned char code crc8_data []
static unsigned long _systime
static unsigned long _uptime
static unsigned char _uptime_cnt
struct {
   unsigned char   mode
   unsigned char   timer
   unsigned char   interval
   unsigned char   n
leds [N_LED]
unsigned short watchdog_timer
unsigned char watchdog_timeout = DEFAULT_WATCHDOG_TIMEOUT
bit watchdog_on

Define Documentation

#define DEFAULT_WATCHDOG_TIMEOUT   10


Function Documentation

unsigned char crc8 ( unsigned char *  buffer,
int  len 
)

00069          : crc8
00070 
00071   Purpose: Calculate 8-bit cyclic redundancy checksum for a full
00072            buffer
00073 
00074   Input:
00075     unsigned char *data     data buffer
00076     int len                 data length in bytes
00077 
00078 
00079   Function value:
00080     unsighend char          CRC-8 code
00081 
00082 \********************************************************************/
00083 {
00084    int i;
00085    unsigned char crc8_code, index;
00086 
00087    crc8_code = 0;
00088    for (i = 0; i < len; i++) {
00089       index = buffer[i] ^ crc8_code;
00090       crc8_code = crc8_data[index];
00091    }
00092 
00093    return crc8_code;
00094 }

unsigned char crc8_add ( unsigned char  crc,
unsigned int  c 
)

00099          : crc8_add
00100 
00101   Purpose: Single calculation for 8-bit cyclic redundancy checksum
00102 
00103   Input:
00104     unsigned char crc       running crc
00105     unsigned char c         new character
00106 
00107 
00108   Function value:
00109     unsighend char          CRC-8 code
00110 
00111 \********************************************************************/
00112 {
00113    unsigned char index;
00114 
00115    index = c ^ crc;
00116    return crc8_data[index];
00117 }

void delay_ms ( unsigned int  ms  ) 

01165 {
01166    unsigned int i;
01167 
01168    for (i = 0; i < ms; i++) {
01169       delay_us(1000);
01170       watchdog_refresh(1);
01171    }
01172 }

void delay_us ( unsigned int  us  ) 

01175 {
01176 #if defined(CPU_C8051F120) || defined(CPU_C8051F310) || defined(CPU_C8051F410)
01177    unsigned char j;
01178 #endif
01179 
01180    unsigned char i;
01181    unsigned int remaining_us;
01182 
01183    if (us <= 250) {
01184       for (i = (unsigned char) us; i > 0; i--) {
01185 #if defined(SCS_210)
01186          _nop_();
01187          for (j=3 ; j>0 ; j--)
01188             _nop_();
01189 #elif defined(CPU_C8051F120)
01190          for (j=22 ; j>0 ; j--)
01191              _nop_();
01192 #elif defined(CPU_C8051F310) || defined(CPU_C8051F410)
01193          _nop_();
01194          for (j=3 ; j>0 ; j--)
01195             _nop_();
01196 #elif defined(CPU_C8051F320)
01197          _nop_();
01198          _nop_();
01199 #else
01200          _nop_();
01201 #endif
01202       }
01203    } else {
01204       remaining_us = us;
01205       while (remaining_us > 250) {
01206          delay_us(250);
01207          remaining_us -= 250;
01208       }
01209       if (us > 0)
01210          delay_us(remaining_us);
01211    }
01212 }

void eeprom_erase ( void   ) 

01321          : eeprom_erase
01322 
01323   Purpose: Erase parameter EEPROM page
01324 
01325 \********************************************************************/
01326 {
01327    unsigned char idata i;
01328    unsigned char xdata * idata p;
01329    unsigned int tmp;
01330    if (_flkey != 0xF1)
01331       return;
01332 
01333    DISABLE_INTERRUPTS;
01334    watchdog_disable();
01335 
01336 #ifdef CPU_C8051F120
01337    SFRPAGE = LEGACY_PAGE;
01338 #endif
01339 
01340 //-PAA
01341    RSTSRC = 0x06; // Enable Missing Clock & VDDMON as reset
01342 
01343 #if defined(CPU_C8051F000)
01344    FLSCL = (FLSCL & 0xF0) | 0x08;       // set timer for 11.052 MHz clock
01345 #elif defined(CPU_C8051F020) || defined(CPU_C8051F120)
01346    FLSCL = FLSCL | 1;                   // enable flash writes
01347 #endif
01348    PSCTL = 0x03;                        // allow write and erase
01349 
01350 #if defined(CPU_C8051F310) || defined(CPU_C8051F320) || defined(CPU_C8051F410)
01351    p = EEPROM_OFFSET;
01352    for (i=0 ; i<N_EEPROM_PAGE ; i++) {
01353       FLKEY = 0xA5;                        // write flash key code
01354       FLKEY = _flkey;
01355 #if defined(CPU_c8051F410)
01356    VDM0CN = 0xA0;
01357    RSTSRC = 0x02; 
01358 #endif
01359    *p = 0;                              // erase page
01360       watchdog_refresh(1);
01361       p += 512;
01362    }
01363 #else
01364    p = EEPROM_OFFSET;
01365    for (i=0 ; i<N_EEPROM_PAGE ; i++) {
01366       *p = 0; // erase page
01367       watchdog_refresh(1);
01368       p += 512;
01369    }
01370 #endif
01371 
01372    PSCTL = 0x00;                        // don't allow write
01373    FLSCL = FLSCL & 0xF0;
01374 
01375    ENABLE_INTERRUPTS;
01376    watchdog_enable(0);
01377 }

void eeprom_flash ( void   ) 

01384          : eeprom_flash
01385 
01386   Purpose: Write system and user parameters to EEPROM
01387 
01388 \********************************************************************/
01389 {
01390    unsigned char i, adr;
01391    unsigned short magic, offset;
01392 
01393    eeprom_erase();
01394 
01395    offset = 0;
01396 
01397    // system info (node address etc...)
01398    eeprom_write(&sys_info, sizeof(SYS_INFO), &offset);
01399 
01400    // magic
01401    magic = 0x1234;
01402    eeprom_write(&magic, 2, &offset);
01403 
01404    // user channel variables
01405    for (adr = 0 ; adr < _n_sub_addr ; adr++)
01406       for (i = 0; variables[i].width; i++)
01407          eeprom_write((char *)variables[i].ud + _var_size*adr,
01408                       variables[i].width, &offset);
01409 
01410    // magic
01411    magic = 0x1234;
01412    eeprom_write(&magic, 2, &offset);
01413 
01414    _flkey = 0;
01415 }

void eeprom_read ( void *  dst,
unsigned char  len,
unsigned short *  offset 
)

01221          : eeprom_read
01222 
01223   Purpose: Read from internal EEPROM
01224 
01225   Input:
01226     unsigned char idata *dst    Destination in IDATA memory
01227     unsigned char len           Number of bytes to copy
01228     unsigend char *offset       Offset in EEPROM in bytes, gets
01229                                 adjusted after read
01230 
01231 \********************************************************************/
01232 {
01233    unsigned char i;
01234    unsigned char code *p;
01235    unsigned char *d;
01236 
01237    watchdog_refresh(1);
01238 
01239    p = EEPROM_OFFSET + *offset;        // read from 128-byte EEPROM page
01240    d = dst;
01241 
01242    for (i = 0; i < len; i++)
01243       d[i] = p[i];
01244 
01245    *offset += len;
01246 }

unsigned char eeprom_retrieve ( unsigned char  flag  ) 

01422          : eeprom_retrieve
01423 
01424   Purpose: Retrieve system and user parameters from EEPROM
01425 
01426 \********************************************************************/
01427 {
01428    unsigned char i, adr, status;
01429    unsigned short magic, offset;
01430 
01431    offset = 0;
01432    status = 0;
01433 
01434    // system info (node address etc...)
01435    eeprom_read(&sys_info, sizeof(SYS_INFO), &offset);
01436 
01437    // check for first magic
01438    eeprom_read(&magic, 2, &offset);
01439    if (magic == 0x1234)
01440       status |= (1 << 0);
01441 
01442    // user channel variables
01443    if (flag) {
01444       for (adr = 0 ; adr < _n_sub_addr ; adr++)
01445          for (i = 0; variables[i].width; i++)
01446             eeprom_read((char *)variables[i].ud + _var_size*adr,
01447                         variables[i].width, &offset);
01448    
01449       // check for second magic
01450       eeprom_read(&magic, 2, &offset);
01451       if (magic == 0x1234)
01452          status |= (1 << 1);
01453    } else
01454       status |= (1 << 1);
01455 
01456    return status;
01457 }

void eeprom_write ( void *  src,
unsigned char  len,
unsigned short *  offset 
)

01253          : eeprom_write
01254 
01255   Purpose: Read from internal EEPROM
01256 
01257   Input:
01258     unsigned char idata *src    Source in IDATA memory
01259     unsigned char len           Number of bytes to copy
01260     unsigend char offset        Offset in EEPROM in bytes, gets
01261                                 adjusted after write
01262 
01263 \********************************************************************/
01264 {
01265    unsigned char xdata * idata p;      // xdata pointer causes MOVX command
01266    unsigned char idata i, b;
01267    unsigned char * idata s;
01268 
01269    if (_flkey != 0xF1)
01270       return;
01271 
01272    watchdog_disable();
01273    DISABLE_INTERRUPTS;
01274 
01275 #ifdef CPU_C8051F120
01276    SFRPAGE = LEGACY_PAGE;
01277 #endif
01278 
01279 //-PAA
01280    RSTSRC = 0x06; // Enable Missing Clock & VDDMON as reset
01281 
01282 #if defined(CPU_C8051F000)
01283    FLSCL = (FLSCL & 0xF0) | 0x08;  // set timer for 11.052 MHz clock
01284 #elif defined(CPU_C8051F020) || defined(CPU_C8051F120)
01285    FLSCL = FLSCL | 1;           // enable flash writes
01286 #endif
01287    PSCTL = 0x01;                // allow write
01288 
01289    p = EEPROM_OFFSET + *offset;
01290    s = src;
01291 
01292    for (i = 0; i < len; i++) {  // write data
01293       b = *s++;
01294 
01295 #if defined(CPU_C8051F310) || defined(CPU_C8051F320) || defined(CPU_C8051F410)
01296       FLKEY = 0xA5;             // write flash key code
01297       FLKEY = _flkey;
01298 #endif
01299 
01300 #if defined(CPU_c8051F410)
01301    VDM0CN = 0xA0;
01302    RSTSRC = 0x02; 
01303 #endif
01304       *p++ = b;
01305    }
01306 
01307    PSCTL = 0x00;                // don't allow write
01308    FLSCL = FLSCL & 0xF0;
01309 
01310    *offset += len;
01311 
01312    ENABLE_INTERRUPTS;
01313    watchdog_enable(0);
01314 }

void led_blink ( unsigned char  led,
unsigned char  n,
int  interval 
)

00871          : blink led
00872 
00873   Purpose: Blink primary or secondary LED for a couple of times
00874 
00875   Input:
00876     int led               0 for primary, 1 for secondary, ...
00877     int interval          Blink interval in ms
00878     int n                 Number of blinks
00879 
00880 \********************************************************************/
00881 {
00882    if (led < N_LED) {
00883       if (leds[led].n == 0 && leds[led].timer == 0) {
00884          leds[led].n = n*2+1;
00885          leds[led].interval = interval / 10;
00886          leds[led].timer = 0;
00887       }
00888    }
00889 }

void led_int (  ) 

00780 {
00781 unsigned char led_i;
00782 
00783    /* manage blinking LEDs */
00784    for (led_i=0 ; led_i<N_LED ; led_i++) {
00785       if (leds[led_i].n > 0 && leds[led_i].timer == 0) {
00786          if ((leds[led_i].n & 1) && leds[led_i].n > 1)
00787             led_set(led_i, LED_ON);
00788          else
00789             led_set(led_i, LED_OFF);
00790 
00791          leds[led_i].n--;
00792          if (leds[led_i].n)
00793             leds[led_i].timer = leds[led_i].interval;
00794       }
00795 
00796       if (leds[led_i].timer)
00797          leds[led_i].timer--;
00798 
00799       if (leds[led_i].n == 0)
00800          led_set(led_i, LED_OFF);
00801    }
00802 }

void led_mode ( unsigned char  led,
unsigned char  flag 
)

00852          : led_mode
00853 
00854   Purpose: Set LED mode
00855 
00856   Input:
00857     int led               0 for primary, 1 for secondary
00858     int flag              Noninverted (0) / Inverted (1)
00859 
00860 \********************************************************************/
00861 {
00862    if (led < N_LED)
00863       leds[led].mode = flag;
00864 }

void led_set ( unsigned char  led,
unsigned char  flag 
)

00894 {
00895    /* invert on/off if mode == 1 */
00896    if (led < N_LED && leds[led].mode)
00897       flag = !flag;
00898 
00899 #ifdef LED_0
00900    if (led == 0)
00901       led_0 = flag;
00902 #endif
00903 #ifdef LED_1
00904    if (led == 1)
00905       led_1 = flag;
00906 #endif
00907 #ifdef LED_2
00908    if (led == 2)
00909       led_2 = flag;
00910 #endif
00911 #ifdef LED_3
00912    if (led == 3)
00913       led_3 = flag;
00914 #endif
00915 #ifdef LED_4
00916    if (led == 4)
00917       led_4 = flag;
00918 #endif
00919 #ifdef LED_5
00920    if (led == 5)
00921       led_5 = flag;
00922 #endif
00923 #ifdef LED_6
00924    if (led == 6)
00925       led_6 = flag;
00926 #endif
00927 #ifdef LED_7
00928    if (led == 7)
00929       led_7 = flag;
00930 #endif
00931 #ifdef LED_8
00932    if (led == 8)
00933       led_8 = flag;
00934 #endif
00935 #ifdef LED_9
00936    if (led == 9)
00937       led_9 = flag;
00938 #endif
00939 }

void sysclock_init ( void   ) 

00742          : sysclock_init
00743 
00744   Purpose: Initial sytem clock via timer 0
00745 
00746 *********************************************************************/
00747 {
00748    EA = 1;                      // general interrupt enable
00749    ET0 = 1;                     // Enable Timer 0 interrupt
00750    PT1 = 0;                     // Interrupt priority low
00751 
00752 #ifdef CPU_C8051F120
00753    SFRPAGE = TIMER01_PAGE;
00754 #endif
00755 
00756    TMOD = (TMOD & 0x0F) | 0x01; // 16-bit counter
00757 #if defined(SCS_210)
00758    CKCON = 0x02;                // use SYSCLK/48
00759    TH0 = 0xEC;                  // load initial value (24.5 MHz SYSCLK)
00760 #elif defined(CPU_C8051F120)
00761    CKCON = 0x02;                // use SYSCLK/48 (98 MHz SYSCLK)
00762    TH0 = 0xAF;                  // load initial value
00763 #elif defined(CPU_C8051F310) || defined(CPU_C8051F410)
00764    CKCON = 0x00;                // use SYSCLK/12
00765    TH0 = 0xAF;                  // load initial value (24.5 MHz SYSCLK)
00766 #else
00767    CKCON = 0x00;                // use SYSCLK/12
00768    TH0 = 0xDB;                  // load initial value
00769 #endif
00770 
00771    TL0 = 0x00;
00772    TR0 = 1;                     // start timer 0
00773 
00774    sysclock_reset();
00775 }

void sysclock_reset ( void   ) 

00716          : sysclock_reset
00717 
00718   Purpose: Reset system clock and uptime counter
00719 
00720 *********************************************************************/
00721 {
00722    unsigned char i;
00723 
00724    _systime = 0;
00725    _uptime = 0;
00726    _uptime_cnt = 100;
00727 
00728    for (i=0 ; i<N_LED ; i++) {
00729      leds[i].mode = 0;
00730      leds[i].timer = 0;
00731      leds[i].interval = 0;
00732      leds[i].n = 0;
00733    }
00734 }

void tcp_timer ( void   ) 

unsigned long time ( void   ) 

00946          : time
00947 
00948   Purpose: Return system time in units of 10ms
00949 
00950 \********************************************************************/
00951 {
00952    unsigned long t;
00953 
00954    DISABLE_INTERRUPTS;
00955    t = _systime;
00956    ENABLE_INTERRUPTS;
00957    return t;
00958 }

void uart_init ( unsigned char  port,
unsigned char  baud 
)

00447          : uart_init
00448 
00449   Purpose: Initialize serial interface, user Timer 1 for UART0 and
00450            (optionally) Timer 2 (4 for F020) for UART1
00451 
00452   Input:
00453     unsigned char baud
00454       1:    2400
00455       2:    4800
00456       3:    9600
00457       4:   19200
00458       5:   28800
00459       6:   38400
00460       7:   57600
00461       8:  115200
00462       9:  172800
00463      10:  345600
00464 
00465 \********************************************************************/
00466 {
00467 #if defined (CPU_C8051F310) || defined(CPU_C8051F410)          // 24.5 MHz
00468    unsigned char code baud_table[] =
00469      {0x100 - 0,    //  N/A
00470       0x100 - 0,    //  N/A
00471       0x100 - 0,    //  N/A
00472       0x100 - 0,    //  N/A
00473       0x100 - 0,    //  N/A
00474       0x100 - 0,    //  N/A
00475       0x100 - 213,  //  57600
00476       0x100 - 106,  // 115200
00477       0x100 - 71,   // 172800
00478       0x100 - 35 }; // 345600
00479 #elif defined(CPU_C8051F320)          // 12 MHz
00480    unsigned char code baud_table[] =
00481      {0x100 - 0,    //  N/A
00482       0x100 - 0,    //  N/A
00483       0x100 - 0,    //  N/A
00484       0x100 - 0,    //  N/A
00485       0x100 - 208,  //  28800
00486       0x100 - 156,  //  38400
00487       0x100 - 104,  //  57600
00488       0x100 - 52,   // 115200
00489       0x100 - 35,   // 172800  2% error
00490       0x100 - 17 }; // 345600  2% error
00491 #elif defined(SCS_210)                // 24.5 MHz
00492    unsigned char code baud_table[] =  // UART0 via timer 2
00493      {0x100 - 0,    //  N/A
00494       0x100 - 0,    //  N/A
00495       0x100 - 160,  //   9600  0.3% error
00496       0x100 - 80,   //  19200  0.3% error
00497       0x100 - 53,   //  28800  0.3% error
00498       0x100 - 40,   //  38400  0.3% error
00499       0x100 - 27,   //  57600  1.5% error
00500       0x100 - 13,   // 115200  2.2% error
00501       0x100 - 9,    // 172800  1.5% error
00502       0x100 - 0 };  // N/A
00503    unsigned char code baud_table1[] = // UART1 via timer 1
00504      {0x100 - 106,  //   2400  0.3% error
00505       0x100 - 53,   //   4800  0.3% error
00506       0x100 - 27,   //   9600  1.5% error
00507       0x100 - 13,   //  19200  2.2% error
00508       0x100 - 9,    //  28800  1.5% error
00509       0x100 - 7,    //  38400  5.1% error
00510       0x100 - 0,    //  N/A
00511       0x100 - 0,    //  N/A
00512       0x100 - 0,    //  N/A
00513       0x100 - 0};   //  N/A
00514 #elif defined(SUBM_260)                // 49 MHz
00515    unsigned char code baud_table[] =  // UART0 via timer 2
00516      {0xFB, 0x100 - 252,  //   2400
00517       0xFD, 0x100 - 126,  //   4800
00518       0xFE, 0x100 - 63,   //   9600
00519       0xFF, 0x100 - 160,  //  19200  0.3% error
00520       0xFF, 0x100 - 106,  //  28800  0.3% error
00521       0xFF, 0x100 - 80,   //  38400  0.3% error
00522       0xFF, 0x100 - 53,   //  57600  0.3% error
00523       0xFF, 0x100 - 27,   // 115200  1.5% error
00524       0xFF, 0x100 - 18,   // 172800  1.5% error
00525       0xFF, 0x100 - 9 };  // 345600  1.5% error
00526 #elif defined(CPU_C8051F120)          // 98 MHz
00527    unsigned char code baud_table[] =  // UART0 via timer 2
00528      {0x100 - 0,    //  N/A
00529       0x100 - 0,    //  N/A
00530       0x100 - 0,    //  N/A
00531       0x100 - 0,    //  N/A
00532       0x100 - 213,  //  28800  0.2% error
00533       0x100 - 160,  //  38400  0.3% error
00534       0x100 - 106,  //  57600  0.3% error
00535       0x100 - 53,   // 115200  0.3% error
00536       0x100 - 35,   // 172800  1.3% error
00537       0x100 - 18 }; // 345600  1.6% error
00538 #if defined(UART1_MSCB) || defined(UART1_DEVICE)
00539    unsigned char code baud_table1[] = // UART1 via timer 1
00540      {0x100 - 0,    //  N/A
00541       0x100 - 212,  //   4800  0.3% error
00542       0x100 - 106,  //   9600  0.3% error
00543       0x100 - 53,   //  19200  0.3% error
00544       0x100 - 35,   //  28800  1.3% error
00545       0x100 - 27,   //  38400  1.6% error
00546       0x100 - 18,   //  57600  1.6% error
00547       0x100 - 9,    // 115200  1.6% error
00548       0x100 - 6,    // 172800  1.6% error
00549       0x100 - 3 };  // 345600  1.6% error
00550 #endif
00551 #else                                 // 11.0592 MHz
00552    unsigned char code baud_table[] =
00553      {0x100 - 144,  //   2400
00554       0x100 - 72,   //   4800
00555       0x100 - 36,   //   9600
00556       0x100 - 18,   //  19200
00557       0x100 - 12,   //  28800
00558       0x100 - 9,    //  38400
00559       0x100 - 6,    //  57600
00560       0x100 - 3,    // 115200
00561       0x100 - 2,    // 172800
00562       0x100 - 1 };  // 345600
00563 #endif
00564 
00565    if (port == 0) { /*---- UART0 ----*/
00566 
00567 #ifdef CPU_C8051F120
00568       SFRPAGE = UART0_PAGE;
00569 #endif
00570 
00571       SCON0 = 0xD0;                // Mode 3, 9 bit, receive enable
00572 
00573 #ifdef CPU_C8051F120
00574 
00575       SFRPAGE = UART0_PAGE;
00576       SSTA0 = 0x15;                // User Timer 2 for baud rate, div2 disabled
00577 
00578       SFRPAGE = TMR2_PAGE;
00579       TMR2CF = 0x08;               // use system clock for timer 2
00580 #ifdef SUBM_260
00581       RCAP2H = baud_table[(baud - 1)*2];    // load high byte
00582       RCAP2L = baud_table[(baud - 1)*2+1];  // load low byte
00583 #else
00584       RCAP2H = 0xFF;
00585       RCAP2L = baud_table[baud - 1];
00586 #endif
00587       TMR2CN = 0x04;               // start timer 2
00588       SFRPAGE = UART0_PAGE;
00589 
00590 #else // CPU_C8051F120
00591 
00592       TMOD  = (TMOD & 0x0F)| 0x20; // Timer 1 8-bit counter with auto reload
00593 
00594 #if defined(CPU_C8051F310) || defined(CPU_C8051F320) || defined(CPU_C8051F410)
00595       CKCON |= 0x08;               // use system clock
00596 #else
00597       T2CON &= ~30;                // User Timer 1 for baud rate
00598       CKCON |= 0x10;               // use system clock
00599 #endif
00600 
00601       TH1 = baud_table[baud - 1];  // load initial values
00602       TR1 = 1;                     // start timer 1
00603 
00604 #endif // CPU_C8051F120
00605 
00606       ES0 = 1;                     // enable serial interrupt
00607       PS0 = 0;                     // serial interrupt low priority
00608 
00609 
00610 #if defined(UART1_MSCB) || defined(UART1_DEVICE)
00611 
00612    } else { /*---- UART1 ----*/
00613 
00614 #if defined(CPU_C8051F020)
00615       SCON1 = 0x50;                // Mode 1, 8 bit, receive enable
00616 
00617       T4CON = 0x34;                // timer 4 RX+TX mode
00618       RCAP4H = 0xFF;
00619       RCAP4L = baud_table[baud - 1];
00620 
00621       EIE2 |= 0x40;                // enable serial interrupt
00622       EIP2 &= ~0x40;               // serial interrupt low priority
00623 
00624 
00625 #elif defined(SCS_210)             // 24.5 MHz
00626       SFRPAGE = UART1_PAGE;
00627       SCON1 = 0x50;                // Mode 1, 8 bit, receive enable
00628 
00629       SFRPAGE = TIMER01_PAGE;
00630       TMOD  = (TMOD & 0x0F)| 0x20; // Timer 1 8-bit counter with auto reload
00631       CKCON = 0x02;                // use SYSCLK/48 (needed by timer 0)
00632 
00633       TH1 = baud_table1[baud - 1];
00634       TR1 = 1;                     // start timer 1
00635 
00636       EIE2 |= 0x40;                // enable serial interrupt
00637       EIP2 &= ~0x40;               // serial interrupt low priority
00638 #elif defined(CPU_C8051F120)       // 98 MHz
00639       SFRPAGE = UART1_PAGE;
00640 #ifdef UART1_MSCB
00641       SCON1 = 0xD0;                // Mode 3, 9 bit, receive enable
00642 #else
00643       SCON1 = 0x50;                // Mode 1, 8 bit, receive enable
00644 #endif
00645 
00646       SFRPAGE = TIMER01_PAGE;
00647       TMOD  = (TMOD & 0x0F)| 0x20; // Timer 1 8-bit counter with auto reload
00648       CKCON = 0x02;                // use SYSCLK/48 (needed by timer 0)
00649 
00650       TH1 = baud_table1[baud - 1];
00651       TR1 = 1;                     // start timer 1
00652 
00653       EIE2 |= 0x40;                // enable serial interrupt
00654       EIP2 |= 0x40;                // serial interrupt high priority, needed in order not
00655                                    // to loose data during UART0 communication
00656 #endif
00657 
00658       uart1_init_buffer();
00659 #endif // defined(UART1_MSCB) || defined(UART1_DEVICE)
00660    }
00661 
00662    EA = 1;                         // general interrupt enable
00663 }

unsigned long uptime ( void   ) 

00965          : uptime
00966 
00967   Purpose: Return system uptime in seconds
00968 
00969 \********************************************************************/
00970 {
00971    unsigned long t;
00972 
00973    DISABLE_INTERRUPTS;
00974    t = _uptime;
00975    ENABLE_INTERRUPTS;
00976    return t;
00977 }

void watchdog_disable ( void   ) 

01099          : watchdog_disable
01100 
01101   Purpose: Disables watchdog
01102 
01103 \********************************************************************/
01104 {
01105 #ifdef USE_WATCHDOG
01106    watchdog_on = 0;
01107    watchdog_timer = 0;
01108 #endif
01109 
01110 #if defined(CPU_C8051F310) || defined(CPU_C8051F320) || defined(CPU_C8051F410)
01111    PCA0MD = 0x00;
01112 #else
01113    WDTCN  = 0xDE;
01114    WDTCN  = 0xAD;
01115 #endif
01116 }

void watchdog_enable ( unsigned char  timeout  ) 

01039          : watchdog_enable
01040 
01041   Purpose: Enables watchdog
01042 
01043   Input:
01044     unsigned char timeout    Watchdog timeout in seconds
01045 
01046 \********************************************************************/
01047 {
01048    if (timeout);
01049 #ifdef USE_WATCHDOG
01050 
01051    watchdog_on = 1;
01052    watchdog_timer = 0;
01053    if (timeout)
01054       watchdog_timeout = timeout;
01055    else
01056       watchdog_timeout = DEFAULT_WATCHDOG_TIMEOUT;
01057 
01058 #ifndef EXT_WATCHDOG
01059 #if defined(CPU_C8051F310) || defined(CPU_C8051F320) || defined(CPU_C8051F410)
01060 #if defined(CPU_C8051F410)
01061    PCA0MD   = 0x00;             // disable watchdog
01062    PCA0CPL5 = 255;              // 65.5 msec @ 12 MHz
01063    PCA0MD   = 0x40;             // enable watchdog
01064    PCA0CPH5 = 0x00;             // reset watchdog
01065 
01066    RSTSRC   = 0x06;             // enable missing clock detector and 
01067 #else                                // VDD monitor as reset source
01068    PCA0MD   = 0x00;             // disable watchdog
01069    PCA0CPL4 = 255;              // 65.5 msec @ 12 MHz
01070    PCA0MD   = 0x40;             // enable watchdog
01071    PCA0CPH4 = 0x00;             // reset watchdog
01072 
01073    RSTSRC   = 0x06;             // enable missing clock detector and 
01074                                 // VDD monitor as reset source
01075 #endif
01076 #else /* CPU_C8051F310 */
01077 
01078    WDTCN    = 0x07;             // 95 msec (11.052 MHz) / 21msec (49 MHz)
01079    WDTCN    = 0xA5;             // start watchdog
01080 
01081 #if defined(CPU_C8051F120)
01082    SFRPAGE = LEGACY_PAGE;
01083    RSTSRC  = 0x06;              // enable missing clock detector & VDDMON
01084 #else
01085    OSCICN |= 0x80;              // enable missing clock detector
01086    RSTSRC  = 0x0B;              // enable reset pin and watchdog reset & VDDMON
01087 #endif
01088 
01089 #endif /* not CPU_C8051F310 */
01090 #endif /* not EXT_WATCHDOG */
01091 #endif /* USE_WATCHDOG */
01092 }

void watchdog_int ( void   ) 

00812          : timer0_int
00813 
00814   Purpose: Timer 0 interrupt routine for 100Hz system clock
00815 
00816            Reload value = 0x10000 - 0.01 / (11059200/12)
00817 
00818 \********************************************************************/
00819 {
00820 #ifdef SUBM_260
00821    tcp_timer();
00822 #else /* SUBM_260 */
00823 
00824 #if defined(SCS_210)
00825    TH0 = 0xEC;                  // for 24.5 MHz clock / 48
00826 #elif defined(CPU_C8051F120)
00827    TH0 = 0xAF;                  // for 98 MHz clock   / 48
00828 #elif defined(CPU_C8051F310) || defined(CPU_C8051F410)
00829    TH0 = 0xAF;                  // for 24.5 MHz clock / 12 
00830 #else
00831    TH0 = 0xDC;                  // reload timer values, let LSB freely run
00832 #endif
00833 
00834 #endif /* !SUBM_260 */
00835    _systime++;                  // increment system time
00836    _uptime_cnt--;
00837    if (_uptime_cnt == 0) {      // once every second
00838       _uptime++;
00839       _uptime_cnt = 100;
00840    }
00841    
00842    led_int();
00843    watchdog_int();
00844 }

void watchdog_refresh ( unsigned char  from_interrupt  ) 

00991          : watchdog_refresh
00992 
00993   Purpose: Resets watchdog, has to be called regularly, otherwise
00994            the watchdog issues a reset. If called from an interrupt
00995            routine, just reset the hardware watchdog, but not the
00996            watchdog timer. Reset the watchdog timer only when called
00997            from the user loop, to ensure that the main user loop
00998            is running.
00999 
01000   Input:
01001     unsigned char from_interrupt  0 if called from normal user loop,
01002                                   1 if called from interrupt routine
01003 
01004 
01005 \********************************************************************/
01006 {
01007    if (from_interrupt);
01008 
01009 #ifdef USE_WATCHDOG
01010    if (from_interrupt == 0)
01011       watchdog_timer = 0;
01012 
01013    if (watchdog_on && watchdog_timer < watchdog_timeout*100) {
01014 
01015 #ifdef EXT_WATCHDOG
01016       EXT_WATCHDOG_PIN = !EXT_WATCHDOG_PIN;
01017 #else
01018 #if defined(CPU_C8051F310) || defined(CPU_C8051F320) || defined(CPU_C8051F410)
01019 #if defined(CPU_C8051F410)
01020       PCA0CPH5 = 0x00;
01021 #else
01022       PCA0CPH4 = 0x00;
01023 #endif
01024 #else
01025       WDTCN = 0xA5;
01026 #endif
01027 #endif // EXT_WATCHDOG
01028 
01029    }
01030    
01031 #endif
01032 }


Variable Documentation

unsigned char idata _flkey

unsigned char idata _n_sub_addr

unsigned long _systime [static]

unsigned long _uptime [static]

unsigned char _uptime_cnt [static]

unsigned char idata _var_size

unsigned char code crc8_data[]

unsigned char interval

struct { ... } leds[N_LED]

unsigned char mode

unsigned char n

SYS_INFO sys_info

unsigned char timer

MSCB_INFO_VAR* variables

bit watchdog_on

unsigned char watchdog_timeout = DEFAULT_WATCHDOG_TIMEOUT

unsigned short watchdog_timer


Generated on 10 Jun 2013 for FGDC8051 by  doxygen 1.4.7